Semiconductor device and method of manufacturing a semiconductor device

ABSTRACT

A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-96499, filed on Apr. 2,2007, the entire content of which is incorporated herein by reference.

BACKGROUND

In a semiconductor device, a shallow trench isolation (STI) method ofburying an insulator in a trench formed in a semiconductor substrate isgenerally used as a method of electrically isolating elements such astransistors, diodes, trench capacitors, or resistors provided over thesemiconductor substrate.

The STI method is known to be capable of achieving a desired elementwithstand voltage. The STI method is described with reference to thedrawings.

FIGS. 1A to 1F are schematic sectional views of a principal portion,illustrating a method of manufacturing a semiconductor device. As shownin FIG. 1A, a silicon oxide film 200 and a silicon nitride film 300 areformed over a semiconductor substrate 100 and then patterned.

As shown in FIG. 1B, the semiconductor substrate 100 is etched using thesilicon nitride film 300 as a mask to form trenches 101. Each of thetrenches 101 has a flat bottom 101 a.

The angle formed by the bottom and the side of each trench 101 isreferred to as a “taper angle α”.

As shown in FIG. 1C, silicon oxide films 101 b are formed over the innerwalls of the trenches 101 by surface thermal oxidation. Then, oxidefilms 400 are formed in the trenches 101 by chemical vapor deposition(CVD) and polished by chemical mechanical polishing (CMP). The materialof the oxide films 400 is a silicon oxide film.

As shown in FIG. 1D, the silicon nitride film 300 and the silicon oxidefilm 200 are removed by chemical treatment or isotropic etching.

As shown in FIG. 1E, p-type metal oxide semiconductor (PMOS) regions 102and n-type metal oxide semiconductor (NMOS) regions 103 are formed bywell implantation. Further, channel regions 104 and 105 are formed bychannel implantation.

As shown in FIG. 1F, a gate oxide film 106 is formed over each of thePMOS regions 102 and the NMOS regions 103, and gate electrodes 107 and108 are then formed. Further, source and drain regions 109 a, 109 b, 110a, and 110 b are formed over the semiconductor substrate 100 to form MOStransistors 111 and 112.

When the trenches 101 are formed in the semiconductor substrate 100 bythe STI method, a semiconductor device 113 having isolated elementregions is manufactured. The trench width decreases with increasing inintegration of a semiconductor device. Therefore, even when the trenchwidth is narrowed, it is necessary to achieve sufficient elementwithstand voltage.

The term “element withstand voltage” represents a voltage differencebetween the source region 109 b and drain region 110 a when a specifiedcurrent flows between the source and drain regions 109 b and 110 a witheach trench 101 provided therebetween as shown in FIG. 1F. Asemiconductor device preferably has a higher withstand voltage.

SUMMARY

According to an aspect of the invention, a semiconductor device has atrench formed in a semiconductor substrate with a first unevenness atthe bottom thereof, and an insulator buried in the trench.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are sectional views showing a method of manufacturing asemiconductor device;

FIG. 2 is a sectional view showing a structure of an oxide film formedin a trench;

FIG. 3 is a sectional view showing a V-shaped trench structure;

FIGS. 4A and 4B are views each illustrating the element withstandvoltage of a semiconductor device provided with a V-shaped trenchstructure based on the position of the trench;

FIG. 5 is a sectional view of a trench formed in a semiconductorsubstrate according to an embodiment of the present invention;

FIGS. 6A to 6H are sectional views showing a method of manufacturing asemiconductor device according to the embodiment of the presentinvention;

FIG. 7 is a graph showing a relation between the height of unevennessand nitrogen flow rate;

FIG. 8 is a graph showing a relation between the taper angle, selectionratio, and nitrogen flow rate;

FIG. 9 is a graph showing a relation between element withstand voltageand trench width;

FIGS. 10A and 10B are sectional views showing a comparison betweendifferent trench structures; and

FIGS. 11A and 11B are sectional views each showing a trench bottom.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 is a schematic sectional view of a principal portion,illustrating a structure of an oxide film formed in a trench by a CVDmethod.

In a trench 110 having a taper angle α near 90 degrees, a void 401 a mayoccur in the trench 110. Therefore, from the viewpoint of avoiding thevoid, the taper angle α is preferably an acute angle, not a right angle.

However, when the taper angle α is made excessively acute while a narrowtrench structure is maintained, a problem as shown in FIG. 3 occurs.FIG. 3 is a schematic sectional view of a principal portion,illustrating a V-shaped trench structure.

Specifically, when the taper angle α is made excessively acute, aV-shaped trench 120 is formed. Such a V-shaped trench 120 has theproblem of decreasing the element withstand voltage.

FIGS. 4A and 4B are schematic sectional views each showing a principalportion of a semiconductor device provided with a V-shaped trenchstructure. An oxide film 402 is formed in a V-shaped trench 120.

The positional margin at a boundary A between a PMOS region and an NMOSregion is decreased due to the V-shape of the trench structure. When thepositional margin is decreased, the boundary A may lie in the PMOSregion side as shown in FIG. 4A or may lie in the NMOS region side asshown in FIG. 4B.

Therefore, as shown by arrows in FIGS. 4A and 4B, a current easily flowsbetween elements, thereby significantly decrease the element withstandvoltage.

FIG. 5 is a schematic sectional view of a principal portion of a trenchstructure formed in a semiconductor substrate. The trench 11 has abottom 11 a having unevenness (roughness). However, such unevenness isnot formed in the upper surface of a semiconductor substrate 10 and inthe side wall of the trench 11. Also, an oxide film 60 is formed in thetrench 11. A thermal oxide film may be formed over the inner wall of thetrench 11.

As illustrated in FIG. 5, the depth d of the trench 11 is the distancefrom the surface of the semiconductor substrate 10 to the top end of theunevenness. The opening width of the trench 11 is W1, and the width ofthe bottom 11 a of the trench 11 is W2. Also, the height of theunevenness of the bottom 11 a is h. Herein, h denotes a difference inheight between a concave portion and a convex portion of the unevenness.In FIG. 5, the depth d of the trench 11 is, for example, 290 nm to 350nm, the width W1 is, for example, 100 nm to 120 nm, and the width W2 is,for example, 45 nm to 55 nm.

The trench 11 is formed by dry-etching the semiconductor substrate 10.For example, the trench 11 having the bottom 11 a with unevenness isformed by controlling at least one parameter of etching conditions.Examples of parameters include an etching gas flow rate ratio, anetching ambient pressure, an electric power applied to an electrode ofan etching apparatus, and a substrate stage temperature.

The method of forming the trench 11 provided with unevenness isdescribed in detail with reference to FIGS. 6A to 6H. In the method ofmanufacturing a semiconductor device, the trench 11 is formed by dryetching under reduced pressure.

For example, the flow rate of chlorine gas, oxygen gas, nitrogen gas,and argon gas, the electric power applied to an upper electrode, thevoltage applied to a lower electrode of an etching apparatus, thepressure of the etching apparatus, or the substrate stage temperature iscontrolled to form unevenness 11 b at the bottom 11 a of the trench 11.

FIGS. 6A to 6C are schematic sectional views of a principal portion,showing respective steps for forming a mask pattern.

As shown in FIG. 6A, a silicon oxide film 20 is formed in a thicknessof, for example, 10 nm over a semiconductor substrate 10 by a thermaloxidation method. The semiconductor substrate 10 is composed of siliconor gallium arsenide.

A silicon nitride film 30 is formed in a thickness of, for example, 100nm over the silicon oxide film 20 by CVD. An antireflective film 40 isformed in a thickness of, for example, 100 nm by spin coating. Further,a photoresist film 50 is selectively disposed over the antireflectionfilm 40 by photolithography. As the photoresist film 50, for example, anargon fluoride (ArF) resist is used. The thickness of the photoresistfilm 50 is, for example, 300 nm.

Then, as shown in FIG. 6B, the antireflection film 40, the siliconnitride film 30, and the silicon oxide film 20 are etched in order usingthe photoresist film 50 as a mask. After the etching, as shown in FIG.6C, the antireflection film 40 and the photoresist film 50 are removedby ashing.

FIGS. 6D to 6F are sectional views showing respective etching and CMPsteps.

As shown in FIG. 6D, the semiconductor substrate 10 is dry-etched in adry etching apparatus using the silicon nitride film 30 as a mask.

The dry etching apparatus is provided with an inductively coupled plasma(ICP) type coiled electrode as an upper electrode, a high-frequency ACvoltage being applied to the upper electrode. Further, a substrate stageis provided below the upper electrode, for mounting the semiconductorsubstrate thereon.

A DC voltage or AC voltage is applied to the substrate stage, and a biaspotential is superposed thereon. Hereinafter, the substrate stage may bereferred to as a “lower electrode” because a voltage is applied to thesubstrate stage. An etching process according to this embodiment may beobtained by an etching apparatus with a configuration other than theabove as the dry etching apparatus.

An etching gas includes chlorine gas and oxygen gas. Chlorine gas issupplied at 100 sccm to the dry etching apparatus in order to etch thesemiconductor substrate 10. Further, oxygen gas is supplied at 10 sccmin order to form a micromask composed of a reaction product containing aSiO bond on a surface to be etched.

The unevenness 11 b is formed at the trench bottom 11 a by etching usingthese two types of gases.

Further, in order to control the unevenness height h of the trenchbottom, the etching gas may include nitrogen gas with chlorine gas andoxygen gas. The flow rate of nitrogen gas is set to, for example, 0 sccmto 30 sccm.

The ambient pressure of etching is set to, for example, 50 mTorr. Forexample, a high-frequency electric power of 1000 W is applied to theupper electrode, and a bias potential of, for example, −500 V, isapplied to the lower electrode. Further, the treatment time is set to,for example, 30 sec, and the substrate stage temperature is set to, forexample, 60° C.

In this etching treatment, first portions of the bottom 11 a of thetrench 11, excluding second portions covered by the micromask, areetched to form the unevenness at the bottom 11 a.

Specifically, for example, the trenches 11 each having a trench depth dof 310 nm and the unevenness height h of several nm to several tens nmare formed in the semiconductor substrate 10. The width of each convexportion of the unevenness 11 b is 30 nm or less.

The height h of the unevenness 11 b can be controlled by etchingconditions. Further, the taper angle α of the trenches 11, and theetching selection ratio between the semiconductor substrate 10 and thesilicon nitride film 30 can also be controlled by the etchingconditions.

As shown in FIG. 6E, in a step subsequent to the dry etching, a thermaloxide film 10 a having a thickness of, for example, 3 nm is formed overthe inner wall of each trench 11. As shown in FIG. 6F, an insulatingfilm 60, for example silicon oxide film, is buried in each of thetrenches 11.

FIGS. 6G and 6H are sectional views of respective transistor formingsteps. After the silicon nitride film 30 and the silicon oxide film 20are removed, as shown in FIG. 6G, PMOS region 10 b and NMOS region 10 care formed by well implantation in the semiconductor substrate 10. Then,channel regions 10 d and 10 e are formed.

Then, as shown in FIG. 6H, a gate oxide film 10 f is formed over each ofthe PMOS region 10 b and the NMOS region 10 c, and further gateelectrodes 13 and 14 are formed. In addition, source and drain regions10 g, 10 h, 10 i, and 10 j are formed over the semiconductor substrate10 to form MOS transistors 15 and 16 over the semiconductor substrate10.

An element isolation structure is adapted for isolating from each otherp-type impurity regions and n-type impurity regions formed in thesemiconductor substrate 10.

A description is made of how the height h of the unevenness 11 b changeswith changes in the nitrogen flow rate as an example of the etchingconditions.

FIG. 7 is a graph showing a relation between the unevenness height andthe nitrogen flow rate in an etching step. The nitrogen flow rate (sccm)is shown as abscissa, and the height h (nm) of the unevenness 11 b isshown as ordinate.

The height h of the unevenness 11 b can be controlled in the range of 4nm to 47 nm by controlling the flow rate of nitrogen gas in the etchinggases. When the thermal oxide film 10 a is formed over the inner wall ofeach of the trenches 11 after forming the trenches, the lower limit ofthe height h of the unevenness 11 b is controlled to be greater than thethickness of the thermal oxide films 10 a.

For example, when the thermal oxide films 10 a of 3 nm in thickness areformed, the nitrogen flow rate in etching is controlled to 30 sccm orless so that the height h of the unevenness is controlled to 4 nm ormore. This control can prevent the unevenness 11 b from disappearing bythe thermal oxide films 10 a even when the thermal oxide film 10 a isformed over the inner wall of each of the trenches 11. Further, whenunevenness is formed in the sidewalls of the trenches 11, the height ofunevenness in the sidewalls is lower than that of unevenness formed atthe bottoms, and is a half or less of the thickness of the thermal oxidefilms 10 a.

A description is made of how the taper angle α and the selection ratiobetween the semiconductor substrate 10 and the silicon nitride film 30changes with changes in the nitrogen flow rate in the etching treatmentshown in FIG. 6D.

FIG. 8 is a graph showing the nitrogen flow rate dependency of the taperangle and selection ratio. In this figure, the nitrogen flow rate (sccm)is shown in the abscissa, the taper angle (degree) is shown in the leftordinate, and the etching election ratio between the semiconductorsubstrate 10 and the silicon nitride film 30 is shown in the rightordinate.

By controlling the flow rate of nitrogen in the etching gases, the taperangle α of the trenches 11 can be controlled in the range of 80° to 90°.

Also, the selection ratio between the semiconductor substrate 10 and thesilicon nitride film 30 can be controlled by controlling the nitrogenflow rate. The taper angle α of a trench having a flat bottom is about80°.

FIG. 9 is a graph showing the trench width dependency of the elementwithstand voltage. In this figure, the trench widths (μm) of threesamples A, B, and C are shown in the abscissa, and the breakdown voltage(V) corresponding to the element withstand voltage is shown in theordinate.

The sample A has a trench depth d of 310 nm and no unevenness at thebottom of a trench. The sample B has a trench depth d of 330 nm and nounevenness at the bottom of a trench. The sample C has a trench depth dof 310 nm and unevenness having a height h of 20 nm at the bottom of atrench.

In a comparison between the samples A and C, the breakdown voltage ofthe sample C having unevenness with a height of 20 nm at the bottom of atrench more increases than the sample A without unevenness while bothsamples have a trench depth d of 310 nm. In particular, this differencebecomes significant in a narrower trench of 0.1 μm or less in width.

In a comparison between the samples C and B, the samples C and B havethe same breakdown voltage with any one of the trench widths while thetrench depth d of the sample C is less than that of the sample B.

When the bottom 11 a of each trench 11 is provided with the unevenness11 b with height h, bottom-up can be made by h at the depth d of thetrench 11. Therefore, the breakdown voltage can be increased by formingthe unevenness 11 b at the bottom 11 a of each of the trenches 11.

The results shown in FIGS. 7 and 8 are based on only the nitrogen flowrate as a condition parameter of etching. However, in this embodiment, acondition parameter is not limited to the nitrogen flow rate. Namely,the semiconductor substrate 10 having the trenches 11 each provided withthe unevenness 11 b at the bottom 11 a thereof can be formed bycontrolling at least one of the flow rate of chlorine gas and oxygen gasand argon gas in the treatment gases, the electric power applied to theupper electrode and the voltage applied to the lower electrode in thedry etching apparatus, the ambient pressure, and the substrate stagetemperature.

Specifically, for example, chlorine gas at 100 sccm, oxygen gas at 10sccm, and nitrogen gas at 10 sccm are introduced into the dry etchingapparatus, and the total pressure of the atmospheric gas is set to, forexample, 50 mTorr. Further, a high-frequency power of 1000 W is applied,a bias potential of −500 V is applied to the lower electrode, and thesubstrate stage temperature is set to 60° C. These conditions areregarded as basic conditions.

On the basis of the basic conditions, at least one condition parameteris controlled within a predetermined range.

Specifically, chlorine gas at 100 sccm to 200 sccm, oxygen gas at 5 sccmto 30 sccm, and nitrogen gas at 0 sccm to 30 sccm are introduced intothe dry etching apparatus, and further argon gas, as a rare gas, isintroduced into these gases in the range of 0 sccm to 100 sccm. Thetotal ambient pressure is set to 20 mTorr to 50 mTorr. In addition, thehigh-frequency power is set to 500 W to 1200 W, the lower electrode isset to −600 V to −200 V, and the substrate stage temperature is set inthe range of 15° C. to 80° C. The dry etching is performed for apredetermined treatment time.

FIGS. 10A and 10B are schematic views illustrating a comparison betweentrench structures. FIG. 10A shows a trench 11 having unevenness 11 b atthe bottom 11 a thereof, and FIG. 10B shows a trench 12 having a flatbottom 12 a.

As shown in FIG. 10A, the depth of the trench can be substantiallyincreased by forming the unevenness 11 b at the bottom 11 a of thetrench 11. For example, when the unevenness 11 b with high h is formedat the bottom 11 a of the trench 11, the depth d of the trench 11 can besubstantially increased by the height h as compared with the trenchshown in FIG. 10B. Namely, the substantial depth of the trench 11 isd1+h. As a result, in a semiconductor device including the trench 11shown in FIG. 10A, the element withstand voltage is increased ascompared with a semiconductor device including the trench 12 shown inFIG. 10B.

Since the element withstand voltage of a semiconductor device includingthe trench 11 shown in FIG. 10A is increased as compared with asemiconductor device including the trench 12 shown in FIG. 10B, acomparison between the two semiconductor devices with the same withstandvoltage indicates that the depth d1 of the trench 11 shown in FIG. 10Ais shallower by the height h of the unevenness 11 b than the depth d2 ofthe trench 12 shown in FIG. 10B.

Therefore, in a comparison between the two semiconductor devices withthe same withstand voltage, the aspect ratio of the trench 11 shown inFIG. 10A can be decreased relative to the trench 12 shown in FIG. 10B.Consequently, an oxide film can be easily buried in the trench structureshown in FIG. 10A.

In the trench 11 shown in FIG. 10A, an oxide film can be easily buriedin the trench 11, and the taper angle α is brought closer to a rightangle.

Therefore, a semiconductor device including the trench 11 shown in FIG.10A has the bottom 11 a having a sufficient area and causes nopositional deviation as described with reference to FIGS. 4A and 4B.Further, an oxide film can be easily buried in the trench 11.

In the process of forming the trench 11 shown in FIG. 10A, as describedabove, a trench 11 having a small aspect ratio may be formed. Therefore,the etching selection ratio of the silicon nitride film 30 to thesemiconductor substrate 10 can be decreased. As a result, readhesion ofsilicon nitride produced in etching to the semiconductor substrate 10can be suppressed. In other words, the method of manufacturing asemiconductor device according to this embodiment can manufacture asemiconductor device in which defects over the substrate due to thesilicon nitride are decreased to improve the quality.

The height h of the unevenness 11 b is preferably 30% or less of thedepth d of the trench 11. FIGS. 11A and 11B are enlarged views eachshowing a trench bottom. In both FIGS. 11A and 11B, unevenness 11 b isformed at the bottom 11 a of a trench 11. Also, the bottom 11 d of theside of the trench 11 is slightly arcuate, and the width of the bottom11 a excluding the bottom 11 d corresponds to the above-described widthw2.

In order to form substantially uniform unevenness 11 b at the bottom 11a of the trench 11 and achieve sufficient element withstand voltage, itis necessary to form at least two convex portions at the bottom 11 a.

For example, as shown in FIG. 11A, a trench 11 having one convex portion11 c has a so-called sub-trench structure at the bottom 11 a thereof.When such a sub-trench structure is formed in the trench 11, an electricfield is concentrated in the sub-trench. Therefore, it is necessary toform at least two convex portions 11 c at the bottom 11 a of the trench11 as shown in FIG. 11B.

In this case, if the section angle of the tip of the convex portion 11 cis, for example, 140 (70×2), the width W3 of the bottom of the convexportion 11 c is as follows:2×h×tan(7°)  (1)A value obtained by dividing the width W2 of the bottom 11 a of thetrench 11 by the equation (1), i.e., the width W3, corresponds to thenumber of convex portions 11 c. The number of convex portions 11 c isrepresented by the following:50÷(2×h×tan(7°))  (2)Since at least two convex portions 11 c are required, the followinginequality is established:50÷(2×h×tan(7°))≧2  (2)This is solved to obtain h≦101 nm.

As described above with reference to FIG. 5, since the depth d of thetrench 11 is 320 nm, the height h of unevenness is about 32% or less ofthe depth d of the trench 11. Namely, when the height h of theunevenness 11 b is 30% or less of the depth d of the trench 11, thetrench having at least two convex portions 11 c can be provided in thesemiconductor substrate 10.

Further, when the height h of the unevenness 11 b is 15% or less of thedepth d of the trench 11, a leakage current between elements issignificantly decreased. Therefore, the height h of the unevenness 11 bat the bottom 11 a of the trench 11 is more preferably 15% or less ofthe depth d of the trench 11.

The above-described values of d, h, W1, W2, and W3 are only examples,and, in the embodiment, d, h, W1, W2, and W3 are not limited to thesevalues.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed, and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. A method of manufacturing a semiconductor device comprising: forminga mask pattern over a semiconductor substrate; forming a trench havingfirst unevenness in the semiconductor substrate by etching using themask pattern; burying an insulator in the trench; forming a first wellhaving a first conductivity type in the semiconductor substrate, forminga first transistor in the first well, forming a second well having asecond conductivity type different from the first conductivity type inthe semiconductor substrate, forming a second transistor in the secondwell, wherein a bottom of the trench includes a plurality of convexportions extending from the bottom of the trench toward a top of thetrench wherein the trench is located between the first well and thesecond well, wherein the first unevenness includes a plurality ofprojections having a different height downward.
 2. The method accordingto claim 1, wherein a first difference in height of the first unevennessis greater than a second difference in height of second unevennessformed in a side wall of the trench.
 3. The method according to claim 2,wherein the first difference in height is 30% or less of a depth of thetrench.
 4. The method according to claim 3, wherein the first differencein height is 4 nm or more.
 5. The method according to claim 2, whereinthe etching is performed using a mixed gas containing chlorine gas andoxygen gas.
 6. The method according to claim 5, wherein the mixed gasfurther contains a nitrogen gas or a rare gas.
 7. The method accordingto claim 2, further comprising forming a thermal oxide film over theside wall of the trench before burying the insulator in the trench. 8.The method according to claim 7, wherein a thickness of the thermaloxide film is less than the first difference in height.
 9. The methodaccording to claim 7, wherein the second difference in height is a halfor less of a thickness of the thermal oxide film.
 10. The methodaccording to claim 1, wherein the etching to form the trench isperformed using a mixed gas containing chlorine gas, oxygen gas andnitrogen gas.
 11. The method according to claim 1, wherein the trenchhas a taper angle with respect to a surface of the semiconductorsubstrate and the taper angle is adjusted by controlling a flow rate ofnitrogen in an etching gas.
 12. The method according to claim 1, whereinthe trench has a taper angle with respect to a surface of thesemiconductor substrate and the taper angle is 80.degree. to 90.degree.13. A method of manufacturing a semiconductor device comprising: forminga mask pattern over a semiconductor substrate; forming a trench havingfirst unevenness in the semiconductor substrate by etching using themask pattern, the trench having a taper angle with respect to a surfaceof the semiconductor substrate; burying an insulator in the trench;forming a first well having a first conductivity type in thesemiconductor substrate, forming a first transistor in the first well,forming a second well having a second conductivity type different fromthe first conductivity type in the semiconductor substrate, forming asecond transistor in the second well, wherein a bottom of the trenchincludes a plurality of convex portions extending from the bottom of thetrench toward a top of the trench wherein the trench is located betweenthe first well and the second well, wherein the taper angle is adjustedby controlling a flow rate of nitrogen in an etching gas.
 14. The methodaccording to claim 13, wherein the first unevenness includes a pluralityof projections having a different height downward.